Core Course offered in the third year of Bachelor of Computer Engineering in Tribhuvan University.
Course Objectives:
Course Objective: • Main objective of this course is to provide the student with the fundamental knowledge about the basic building logical blocks of digital computer systems. • This course also aims at familiarising the student to design aspect of the logic elements of a computer system.
Course Contents:

Digital Computers and Information (4 hrs) Digital Computers, Information Representation, Computer Structure, Generic Computer, Number Systems, Arithmetic Operations, Conversion of Base, Decimal Codes (BCD), Alphanumeric Codes, Parity Bit.

Combinatorial Logic Circuits (8 hrs) Binary logic and logic gates, Boolean Algebra, Standard Forms, (Min Term and Max Term, Sum of Product and Product of Sum Forms), Map Simplification (1,2,3,4 variable kmap, DonotCare Condition), Universal Gates (NAND, NOR, XOR), Integrated Circuits (Levels of Integration, Digital Logic Families, Positive and Negative Logic, Transmission Gates)

Combinatorial Logic Design (8 hrs) Combinatorial Circuits, Design Issues, Analysis Procedure (Derivation of Boolean Function, Derivation of Truth table, Logic Simulation), Design Procedure (Code Converters), Decoders, Encoders, Multiplexers, Binary Adders, Binary Subtractor, Binary Multipliers, Decimal Arithmetic.

Sequential Circuits (8 hrs) Definition, Latches (SR and D), Flip Flops (Master Slave, Edge Triggered), Sequential Circuit Analysis, (Input Equations, State Table, State Diagram, Analysis with JK Flip Flop), Sequential Circuit Design (Design Procedure, Finding State Diagram and State Tables,) Design with D Flip Flops, Design with JK Flip Flops, Flip Flop Excitation Table, Registers (Shift, Serial), Counters (Ripple, Synchronous Binary, BCD)

Memory and Programmable Logic Devices (8 hrs) Random Access Memory, (Write and Read Operations, Timing Diagram, Properties of Memory, RAM IC's,) Array of RAM IC's, Read Only Memory, Programmable Logic Array, Programmable Logic array Devices, Memory Hierarchy, Locality of Reference, Cache Memory, Virtual Memory.

Instruction Set Architecture (8 hrs) Concept, Operation Cycle, Register Set, Operand Addressing (Zero, One, Two, Three Address Instructions), Addressing Modes (Implied, Immediate, RegisterRegister, Direct, Indirect, Relative, Indexed), Instruction set Architecture, Data Transfer Instruction, Stack Instruction, Data Manipulation Instructions, Logical and Bit Manipulation Instruction, Program Control Instructions, Interrupts.

Central Processing Unit (8 hrs) Data Paths and Operations, Register Transfer Operations, Microoperations, Bus Based Transfer The ALU, The CISC Computer (Instruction Set architecture, Data Path Organization, Microprogrammed Control Organization, Microprogram Structure, Micro Routines).

The Input Out Put and Communications (8 hrs) Computer I/O, Peripherals (Key Board, Hard Disk, Graphics Display, I/O transfer Rates, ), I/O interfaces(I/O Bus and interface units, Strobing, Handshaking, ), Serial Communication( Asynchronous Transmission, Synchronous Transmission), Parity Interrupt (Daisy Chain), DMA (Controller and Transfer), I/O processors.
Text Book :

Mano, M. M., Kime, R. C., Logic and Computer Design Fundamentals, 2E, Pearson Education Asia, ISBN8178083345
Reference Books :

Book by M. Morris Mano/ PHI Book by Hamachar/Zakie/ McGraw Hill